PCI-Express is a serial transfer interface in place of PCI bus, by standardizing 3GIO (3rd Generation I/O). At present, “PCI-Express 1.1” and “PCI-Express 2.0” are known as the standards of PCI-Expression. The PCI-Express 2.0 is of an upper class compatible with PCI-Express 1.1, and equipments for PCI-Express 1.1 are connectable to thereto as they are.
In a transmission path (lane) of a minimum configuration in PCI-Express 1.1, a data transfer rate in a full duplex (FDX) communication is 2.5 Gbps in a unidirectional communication and 5.0 Gbps in a bidirectional communication. Also, in a transmission lane in PCI-Express 2.0, the data transfer rate of a full duplex (FDX) communication is 5.0 Gbps in a unidirectional communication and 10 Gbps in a bidirectional communication. However, in a PCI-Express communication, it is necessary to use 10 bits including 2 bits of a clock signal and so forth in order to transmit an 8-bit data. Therefore, an effective data transfer rate is 2.0 Gbps (250 MB/s) in the unidirectional communication and 4.0 Gbps (500 MB/s) in the bidirectional communication in PCI-Express 1.1, and 4 Gbps (500 MB/s) in the unidirectional communication and 8 Gbps (1 GB/s) in the bidirectional communication in PCI-Express 2.0.
In many cases, an actual PCI-Express port includes a bundle of lanes. A PCI-Express port of one lane is referred to as “PCI-Express x1”, and a PCI-Express port of two lanes is referred to as. “PCI-Express x2”. A bundle of a plurality of lanes is referred to as a link. At present, products such as x2, x4, x8, x12, x16 and x32 are commercially available. The PCI-Express is often used as a video card interface because of high-speed performance.
Also, the PCI-Express is compliant with a hot plug and a usage method of setting a cassette-type hardware unit to a computer is available. “PCI-Express x1” as well as “USB 2.0” is used in a communication system of “Express Card” of an expansion card specification applied to a new mobile computer in place of a PC card. Regarding PCI-Express, not only a conventional connecting method of inserting a card into an expansion slot is defined but also a specification of “PCI Express Cable” is defined which can connect between equipments via a metal cable of not longer than 10 meters. In addition, at present, a PCI-Express communication system using PCI-Express appears, in which each module is connected by a PCI-Express switch to thereby communicate between the modules based on PCI-Express.
In conjunction with the above description, Japanese Patent Publication (JP 2006-302250A: patent literature 1) discloses a PCI-Express communication system. In this PCI-Express communication system, a node ID of a transfer destination module, a channel ID for use in data transfer and a packet type for discriminating whether the transfer data is a request or a response are set in an address portion of a packet for the data transfer.
In a network communication system, it is necessary to prepare an alternative route at a time of occurrence of a communication failure.
When a communication system using PCI-Express is built, a target address is uniquely determined for every target device. Therefore, in the communication system using PCI-Express, it is necessary to set a different target address for each communication route. As a feature of PCI-Express, an address space should be continuous for every device in a lower layer. This is because of the PCI-Express specification that only an upper limit and a lower limit of an address can be set in an address space of a specific route, in view of a route complex. Also, the address space of route complex is a whole address space which is not assigned to address spaces of devices in the lower layer. Therefore, in one route complex, the address space allocated to a PCI-Express switch connected to another route complex should be separated for every route in the whole address space.
FIG. 1 shows assignment of address spaces on PCI-Express switches. In FIG. 1, the address spaces are separated between a PCI-Express switch under the control of a route complex (RC) 0 and a PCI-Express switch under the control of a route complex (RC) 4. However, since each address space is assigned to a space of the PCI-Express switch under the control of the other route complex, the address space of the route complex is not contained. Therefore, a packet cannot be transmitted to the other route complex as it is without being processed. In a PCI-Express=PCI-Express bridge, an address conversion function is provided in the bridge to separate the address space for every topology when different topologies are connected. By this address conversion function, it becomes possible to transmit a packet between route complexes having different topologies. In FIG. 2, each packet transmitted from a route complex (RC) 1 is converted to an identical address space different from the address space corresponding to each PCI-Express switch. Since this packet is not assigned to a space which is assigned to the switch, it is transferred to a route complex.
However, when the address conversion function is used, the packet is transmitted to the address space of the same route complex, and therefore it is difficult to determine a transmission route of the packet on a route complex side.
In the patent literature 1, a method is disclosed of giving a node ID of a transmission source device in addition to an address of a transmission destination device. However, it is not defined which route is used for transmission when a plurality of communication routes are present. Also, in the patent literature 1, although an embodiment having two routes is shown, there is no explanation at all how to switch the routes.
When address conversion is performed inside the bridge, it becomes possible to confirm a data transmission route by assigning a different unique address for every route. FIG. 3 shows a case where different addresses are assigned in every bridge. However, when different addresses are assigned to the routes, a final address on reaching a route complex is different. Therefore, there arises a problem that an access to an identical address space is mapped to a different address space.